1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a memory area and a logic circuit area. More specifically the invention pertains to a method of manufacturing a semiconductor device, on which each of non-volatile memory devices formed in the memory area has two charge accumulation regions relative to one word gate.
2. Description of the Related Art
A semiconductor device is constructed by a chip, on which a memory area including memory cells and a logic circuit area including peripheral circuits of memories are mainly formed. The memory area is generally arranged on a central portion of the chip, and the logic circuit area is arranged on a peripheral portion of the chip to surround the memory area.
Chips are arranged in a grid on a semiconductor wafer (semiconductor substrate). There is a scribing area between adjoining chips. The scribing area represents a region of scratch marks on the surface of the wafer, which is used to divide the wafer into the respective chips.
One type of non-volatile semiconductor memory devices is MONOS (Metal Oxide Nitride Oxide Semiconductor) or SONOS (Silicon Oxide Nitride Oxide Silicon), in which a gate insulating layer between a channel area and a control gate is a multi-layered body of a silicon oxide layer and a silicon nitride layer and charges are trapped by the nitride silicon layer.
FIG. 31 shows a known MONOS non-volatile semiconductor memory device (refer to: Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers p.122-123).
Each MONOS memory cell 100 has a word gate 14, which is formed in a memory area on a semiconductor substrate 10 via a first gate insulating layer 12. A first control gate 20 and a second control gate 30 are formed as side walls on both sides of the word gate 14. A second gate insulating layer 22 is present between the bottom of the first control gate 20 and the semiconductor substrate 10. An insulating layer 24 is present between the side face of the first control gate 20 and the word gate 14. Similarly the second gate insulating layer 22 is present between the bottom of the second control gate 30 and the semiconductor substrate 10. The insulating layer 24 is present between the side wall of the second control gate 30 and the word gate 14. Impurity layers 16 and 18, each of which constitutes either a source area or a drain area, are formed in the semiconductor substrate 10 to be located between the control gate 20 and the control gate 30 of adjoining memory cells.
Each memory cell 100 accordingly has two MONOS memory elements on the side faces of the word gate 14. These two MONOS memory elements are controlled independently. Namely each memory cell 100 is capable of storing 2-bit information.
A memory area including such MONOS memory cells and a logic circuit area including peripheral circuits of memories are formed on an identical chip. A prior art method of manufacturing such a chip first forms memory cells in the memory area and subsequently forms peripheral circuits in the logic circuit area. The manufacturing method forms diverse wiring layers via an insulating layer, after formation of the memory area and the logic circuit area.
The manufacturing method forms an insulating layer of, for example, silicon oxide, on the whole surface of the chip and polishes the insulating layer by CMP (chemical mechanical polishing) technique. The polishing is carried out until exposure of stopper layers under the insulating layer in the memory area.
When the insulating layer is formed over the whole surface of the semiconductor substrate, the protrusions appear on the top surface of the insulating layer in the memory area and the logic circuit area on the chip, corresponding to the gate layers and the gate electrodes below the insulating layer. There is no gate layer nor gate electrode, on the other hand, in a scribing area between adjoining chips. Namely the scribing area does not have such protrusions. There is accordingly a variation in polishing rate of the insulating layer. The insulating layer in the scribing area between adjoining chips is polished faster and thereby to a greater degree than the insulating layer in the memory area and the logic circuit area on the chip. A part of the chip close to the scribing area, that is, a peripheral portion of the chip, may thus be polished excessively.
The peripheral portion of the chip is the logic circuit area, as described above. When gate electrodes are present in such an excessively polished portion, the gate electrodes in the logic circuit area may be exposed, prior to exposure of the stopper layers in the memory area, in the process of polishing the insulating layer.
The suicide layer has been formed on the gate electrodes in the precedent process. Exposure of the gate electrodes in the logic circuit area may cause the suicide layer to be polished and contaminate a CMP apparatus used for polishing the insulating layer with metals. The exposed gate electrodes may be etched out in the subsequent process of patterning and forming the word lines by etching.